Meta Media MV-900 Spécifications

1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs Data Sheet AD5560 Rev. D Information furnished by Analog Devices

AD5560 Data Sheet Rev. D | Page 10 of 68 Parameter Min Typ Max Unit Test Conditions/Comments Comparator DAC Dynamic Output Voltage S

Data Sheet AD5560 Rev. D | Page 11 of 68 Parameter Min Typ Max Unit Test Conditions/Comments SPI INTERFACE LOGIC Logic Inputs

AD5560 Data Sheet Rev. D | Page 12 of 68 Parameter Min Typ Max Unit Test Conditions/Comments Power Supply Sensitivity1 DC to 1 kHz. ΔF

Data Sheet AD5560 Rev. D | Page 13 of 68 TIMING CHARACTERISTICS HCAVDDx ≤ AVSS + 33 V, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V

AD5560 Data Sheet Rev. D | Page 14 of 68 SYNCSCLKSDIBUSYRESET12t3t224t4t6t1t7t8t9DB23DB0t10t11t12BUSYt51LOAD ACTIVE DURINGBUSY.2LOAD ACTIVE AFTER BU

Data Sheet AD5560 Rev. D | Page 15 of 68 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating AVDD to AVSS 34 V AVDD to AGND −0.3 V to +34 V AVSS t

AD5560 Data Sheet Rev. D | Page 16 of 68 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NCCF4CF3CF2CF1CF0DUTGNDSENSEEXTMEASILGUARD/SYS_DUTGNDAGNDAVSSA

Data Sheet AD5560 Rev. D | Page 17 of 68 Pin No. Mnemonic Description 18 VREF Reference Input for DAC Channels, Input Range 2 V to 5 V. 19, 44

AD5560 Data Sheet Rev. D | Page 18 of 68 9 8 7 6 5 4 3 2 1EXTFORCE1A EXTFORCE1A EXTFORCE2A EXTFORCE1B EXTFORCE1B EXTFORCE2B EXTFORCE1C EXTFORCE1C GP

Data Sheet AD5560 Rev. D | Page 19 of 68 Pin No. Mnemonic Description D1 TMPALM Temperature Alarm Flag. Open-drain output, active low; this pin ca

AD5560 Data Sheet Rev. D | Page 2 of 68 TABLE OF CONTENTS Features ...

AD5560 Data Sheet Rev. D | Page 20 of 68 TYPICAL PERFORMANCE CHARACTERISTICS 07779-026CODELINEARITY (mV)–0.200.20.40.60.81.01.20 10,000 20,000 30,0

Data Sheet AD5560 Rev. D | Page 21 of 68 07779-037CODE0 10,000 20,000 30,000 40,000 50,000 60,000 70,000HIGH SUPPLIESNOMINAL SUPPLIESHIGH: AVDD = 28

AD5560 Data Sheet Rev. D | Page 22 of 68 07779-032STRESS VOLTAGE (V)LEAKAGE CURRENT (nA)TJ = 25°C–0.20–0.15–0.10–0.050.0500.100.15–10 5 0 5 10EXTFORC

Data Sheet AD5560 Rev. D | Page 23 of 68 –0.007–0.006–0.005–0.004–0.003–0.002–0.001025 35 45 55 65 75 8507779-045TEMPERATURE (°C)GAIN ERROR (%)HIGHN

AD5560 Data Sheet Rev. D | Page 24 of 68 07779-017CH1 50mVCH3 5VM200µs A CH3 1.5V13T 10.4%CH1 p-p159mVCH1 AREA14.31µVsBWBWFORCESYNC Figure

Data Sheet AD5560 Rev. D | Page 25 of 68 CH2 5V07779-023CH1 100mV M40µs A CH2 4.6V12T 120.4µsCH1 p-p174mVBWTRIGGERFORCE Figure 38. Safe Mod

AD5560 Data Sheet Rev. D | Page 26 of 68 07779-058CH1 5VCH3 5VM20µs A CH3 2.9V124T 4.6%BWCH2 1VCH4 10VTA = 25°CAVDD = +16.25VAVSS = –16.2

Data Sheet AD5560 Rev. D | Page 27 of 68 –120–100–80–60–40–20010 100 1k 10k 100k 1M 10M07779-051FREQUENCY (Hz)ACPSRR (dB)MV: GAIN 0FOHMI: GAIN 0DVCC

AD5560 Data Sheet Rev. D | Page 28 of 68 TERMINOLOGY Offset Error Offset error is a measure of the difference between the actual voltage and the ide

Data Sheet AD5560 Rev. D | Page 29 of 68 THEORY OF OPERATION The AD5560 is a single-channel, device power supply for use in semiconductor automatic

Data Sheet AD5560 Rev. D | Page 3 of 68 REVISION HISTORY 8/12—Rev. C to Rev. D Added 72-Ball Flip-Chip BGA (Throughout) ...

AD5560 Data Sheet Rev. D | Page 30 of 68 GPO The GPO pin can be used as an extra control bit for external switching functions, such as for switching

Data Sheet AD5560 Rev. D | Page 31 of 68 resistors to further optimize stability and settling time perform-ance. The AD5560 has three compensation m

AD5560 Data Sheet Rev. D | Page 32 of 68 Master in FV Mode, Slaves in Force Current (FI) Mode The master device is placed into FV mode, and all slav

Data Sheet AD5560 Rev. D | Page 33 of 68 DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN There are three types of temperature sensors in the AD5560. •

AD5560 Data Sheet Rev. D | Page 34 of 68 VMIN is another inportant voltage level that is used in other parts of the circuit. When using a MEASOUT ga

Data Sheet AD5560 Rev. D | Page 35 of 68 attatt5RR1kΩ5RmimvattatttriDACatt1kΩ5RROSD DAC INMEASUREVOLTAGEMEASURECURRENTMEASOUT5RNOTES1. att: ATTENUAT

AD5560 Data Sheet Rev. D | Page 36 of 68 FORCE AMPLIFIER STABILITY There are three modes for configuring the force amplifier: safe mode, autocompensa

Data Sheet AD5560 Rev. D | Page 37 of 68 POLES AND ZEROS IN A TYPICAL SYSTEM Typical closed loop systems have one dominant pole in the feedback path

AD5560 Data Sheet Rev. D | Page 38 of 68 stability problems. This is most likely to be the case when there are both a large CR and large RC. The RP

Data Sheet AD5560 Rev. D | Page 39 of 68 10. Calculate FZ, the ESR zero frequency, using FZ = 1/(2πRcCr). 11. If FP > Fug, the load pole is abo

AD5560 Data Sheet Rev. D | Page 4 of 68 FUNCTIONAL BLOCK DIAGRAM RZ: 500ΩTO 1.6MΩRP: 200ΩTO 1MΩ100kΩ25kΩ6kΩGPORESETAVSSAVDDHW_INH/LOADDGND CLALMTMPA

AD5560 Data Sheet Rev. D | Page 40 of 68 The transfer function for these 16-bit DACs is DUTGNDCODEDACOFFSETVCODEDACVVCLLVCLHREFREF+××−

Data Sheet AD5560 Rev. D | Page 41 of 68 REFERENCE SELECTION The voltage applied to the VREF pin determines the output voltage range and span applie

AD5560 Data Sheet Rev. D | Page 42 of 68 PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE The exposed pad and leads of the TQFP package have a 100% ti

Data Sheet AD5560 Rev. D | Page 43 of 68 NOWRITE NEWFIN ×1 DAC VALUEUPDATE DACCODE?NOYESNOCHANGE RAM PSTART?NEW RAMPYESCHANGESTEP SIZE?SELECT RAMP S

AD5560 Data Sheet Rev. D | Page 44 of 68 SERIAL INTERFACE The AD5560 contains an SPI-compatible interface operating at clock frequencies of up to 50

Data Sheet AD5560 Rev. D | Page 45 of 68 If Bits[8:7] of the system control register (Address 0x1) are high, then the CLEN and HW_INH operate as no

AD5560 Data Sheet Rev. D | Page 46 of 68 CONTROL REGISTERS DPS AND DAC ADDRESSING The serial word assignment consists of 24 bits, as shown in Table

Data Sheet AD5560 Rev. D | Page 47 of 68 Table 18. DPS Register 1 Address Default Data Bits, MSB First 0x2 0x0000 Bit Name Function 15 SW-

AD5560 Data Sheet Rev. D | Page 48 of 68 Table 19. DPS Register 2 Address Default Data Bits, MSB First 0x3 0x0000 Bit Name Function 15 SF0 Sy

Data Sheet AD5560 Rev. D | Page 49 of 68 The AD5560 has three compensation modes. The power-on default mode is SAFEMODE enabled. This ensures that t

Data Sheet AD5560 Rev. D | Page 5 of 68 SPECIFICATIONS HCAVDDx ≤ (AVSS + 33 V), HCAVDDx ≤ AVDD, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVS

AD5560 Data Sheet Rev. D | Page 50 of 68 Table 21. Compensation Register 2 Address Default Data Bits, MSB First 0x5 0x0110 Bit Name Function

Data Sheet AD5560 Rev. D | Page 51 of 68 Register 0x6 allows the user to enable or disable any of the alarm flags that are not required. If disabled

AD5560 Data Sheet Rev. D | Page 52 of 68 Table 23. Diagnostic Register Address Default Data Bits, MSB First 0x7 0x0000 Bit Name Function 15

Data Sheet AD5560 Rev. D | Page 53 of 68 Address Default Data Bits, MSB First 0x7 0x0000 Bit Name Function 24 Force amplifier NPNs 1A-1

AD5560 Data Sheet Rev. D | Page 54 of 68 Table 24. Other Registers Address Register Default Data Bits, MSB First 0x8 FIN DAC x1 0x8000 x1 DAC

Data Sheet AD5560 Rev. D | Page 55 of 68 Address Register Default Data Bits, MSB First 0x3C CPH DAC c EXT Range 1 0x8000 D15 to D0. 0x3D DGS

AD5560 Data Sheet Rev. D | Page 56 of 68 Table 25. Alarm Status and Clear Alarm Status Register Address Register Default Data Bits, MSB first 0x4

Data Sheet AD5560 Rev. D | Page 57 of 68 READBACK MODE The AD5560 allows data readback via the serial interface from every register directly accessi

AD5560 Data Sheet Rev. D | Page 58 of 68 Table 26. AD5560 Truth Table of Switches1 Reg Bit Name Bit SW1 SW2 SW3 SW4 SW7 SW13 SW14 SW15 S

Data Sheet AD5560 Rev. D | Page 59 of 68 USING THE HCAVDDx AND HCAVSSx SUPPLIES The first set of power supplies, AVDD and AVSS, provide power to th

AD5560 Data Sheet Rev. D | Page 6 of 68 Parameter Min Typ Max Unit Test Conditions/Comments Measure Current Ranges Specified current ra

AD5560 Data Sheet Rev. D | Page 60 of 68 REQUIRED EXTERNAL COMPONENTS The minimum required external components are shown in the block diagram in Fig

Data Sheet AD5560 Rev. D | Page 61 of 68 POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consid-eration of the power sup

AD5560 Data Sheet Rev. D | Page 62 of 68 APPLICATIONS INFORMATION THERMAL CONSIDERATIONS Table 28. Thermal Resistance for TQFP_EP1 Cooling Airflow

Data Sheet AD5560 Rev. D | Page 63 of 68 TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package Due to localized heating, temperature at

AD5560 Data Sheet Rev. D | Page 64 of 68 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HU10-19-2011-C4964171163233480.50BSCLEAD PITCH12

Data Sheet AD5560 Rev. D | Page 65 of 68 ORDERING GUIDE Model1 Temperature Range2 Package Description Package Option AD5560JSVUZ TJ = 25°C to +90oC

AD5560 Data Sheet Rev. D | Page 66 of 68 NOTES

Data Sheet AD5560 Rev. D | Page 67 of 68 NOTES

AD5560 Data Sheet Rev. D | Page 68 of 68 NOTES ©2008-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are th

Data Sheet AD5560 Rev. D | Page 7 of 68 Parameter Min Typ Max Unit Test Conditions/Comments MEASOUT Gain = 0.2 Linearity Error −5.5

AD5560 Data Sheet Rev. D | Page 8 of 68 Parameter Min Typ Max Unit Test Conditions/Comments SYS_FORCE Voltage Range AVSS AVDD V

Data Sheet AD5560 Rev. D | Page 9 of 68 Parameter Min Typ Max Unit Test Conditions/Comments SETTLING TIME (FV, MEASURE CURRENT) Compensation Re